`PLUS CA change, plus c'est la meme chose', `The more things change, the more they remain the same.'
The irony of having to go back forty years, to one's technological roots, so that one can move forward into the next decade of silicon chip manufacturing, is a powerful and recent illustration of this well known French saying.
Took twenty years
It took almost twenty years after Shockley, Bardeen and Brattain of Bell Labs, co-invented the point contact transistor in December 1947, for architecture of the complementary metal oxide semiconductor or CMOS transistor to become an industry standard: A bedrock semiconductor (usually silicon) substrate where the current flowed; on top of this, a metal oxide (usually silicon dioxide) dielectric which served as an insulator and finally on top of that, a metallic `gate' which turns the device on and off, processing the ones and zeroes that are fundamental to computer calculations.
Quite soon, the metal of the gate (the `M' in MOS) was replaced by non metallic poly-silicon, and so things remained for the next four decades, while chip makers squeezed more and more transistors on every slab of silicon, reducing the gap between active components to 130, 90 and 65 nanometres. (A nanometre is a billionth of a metre).
This has been the state of semiconductor art — till today.
The next logical step in the incredible shrinking saga of chip-making is a fabrication tolerance of 45 nanometres and here a roadblock appears. As the Senior Vice President (Digital Enterprise) explained to me on the sidelines of the Intel Developer Forum in Beijing last week, "the whole industry is having to struggle at 45 nm.
"The Silicon dioxide we have used to make the gate dielectric for 40 years now, has become so thin — as little as 1.2 nanometers thick — that current leakage through the dielectric becomes unacceptably high leading to unnecessary heat loss and waste of energy."
Intel's response has been to take a fresh look at the fundamental way transistors have always been made.
Their engineers found better insulating properties — by a factor of 10 — in a class of materials called `high k' dielectric (`k' is what engineers call the dielectric constant).
They replaced silicon dioxide with hafnium, a rare earth element with atomic number 72 in the Periodic Table, and a material that is used in the control rods of nuclear reactors.
Metallic combo
They found that hafnium could not be made to work with poly silicon gate electrodes and decided to put the 'M' back into MOS. They came up with a metallic combo for the gate material (the exact combination is a secret).
At any rate, reworking the transistor with a high-k dielectric and returning to its roots in a metallic gate has helped Intel make a successful transition to 45 nanometer fabrication with a 20 per cent increase in the drive current and a five fold decrease in leakage.
The result, they can cram twice as many transistors on the 45 nm slab as they could at 65 nm. And cut switching power consumption by a third.
Radically different
The new processor family based on this radically different way of manufacturing transistors is being called `Penryn'— and it will ensure that Moore's Law (which predicted a doubling of transistors on a chip and consequent computational power, every 24 months) lives on.
Dr Moore himself has characterised it as the biggest change in transistor technology since the introduction of poly silicate gate MOS in the late 1960s.
At Beijing, I saw production wafers, 300 mm in diameter, containing thousands of the new 45 nm Penryn class chips — every chip now housing a billion transistors.
By year end, Intel plans to roll out dual and quad core (that is two and four processor cores to a chip) microprocessors in the new 45 nm process, in all three segments: server, desktop and portable PCs.
Prototype machines fuelled by these chips were up and working at the IDF. Intel had struck out into the future by a canny step back to the metallic origins of the transistor.
It is unrealistic to expect that Intel will remain alone for long, while getting past this significant obstacle in the long history of semiconductor manufacturing.
Competitors like AMD, Infineon, Freescale, Sony, Toshiba all have their own technology trails to get to 45 nm and beyond. IBM, has announced its own high-k metal gate technology that should reach the fabs in 2008.
`Garam hawa'
Texas Instruments has also said it has a high-k solution that it will be realising this year. Clearly `Back to the Future' is the way the semiconductor `garam hawa' is blowing this year.
Forty five nanometre technology and the consequent ability to put over a billion active components on every chip, will possibly kick start the tera scale computing initiatives of various players.
Intel's Indian engineers contributed nearly half the effort that went into its recently announced `teraflop on a chip' concept processor with 80 cores on board. Sometimes seeing is the only way to believing.
Just 46 watts
At the Beijing event, I saw Nitin Borkar, Head of Intel's Terascale project, put a machine fuelled by the 80-core chip through its paces — live. As the `flop' meter crossed the 1 tera flop (that is a trillion floating point operations a second) marker, the chip was drawing just 46 watts — less than a light bulb!
At 1.5 teraflops, the energy consumed was 93 watts and finally in a final burst of speed, Nitin had the computer cross the magic 2 tera flop mark dissipating less than 192 watts.
Did they say one teraflop on a chip? So yesterday! Already a month later, it looks more like two.
The irony of having to go back forty years, to one's technological roots, so that one can move forward into the next decade of silicon chip manufacturing, is a powerful and recent illustration of this well known French saying.
Took twenty years
It took almost twenty years after Shockley, Bardeen and Brattain of Bell Labs, co-invented the point contact transistor in December 1947, for architecture of the complementary metal oxide semiconductor or CMOS transistor to become an industry standard: A bedrock semiconductor (usually silicon) substrate where the current flowed; on top of this, a metal oxide (usually silicon dioxide) dielectric which served as an insulator and finally on top of that, a metallic `gate' which turns the device on and off, processing the ones and zeroes that are fundamental to computer calculations.
Quite soon, the metal of the gate (the `M' in MOS) was replaced by non metallic poly-silicon, and so things remained for the next four decades, while chip makers squeezed more and more transistors on every slab of silicon, reducing the gap between active components to 130, 90 and 65 nanometres. (A nanometre is a billionth of a metre).
This has been the state of semiconductor art — till today.
The next logical step in the incredible shrinking saga of chip-making is a fabrication tolerance of 45 nanometres and here a roadblock appears. As the Senior Vice President (Digital Enterprise) explained to me on the sidelines of the Intel Developer Forum in Beijing last week, "the whole industry is having to struggle at 45 nm.
"The Silicon dioxide we have used to make the gate dielectric for 40 years now, has become so thin — as little as 1.2 nanometers thick — that current leakage through the dielectric becomes unacceptably high leading to unnecessary heat loss and waste of energy."
Intel's response has been to take a fresh look at the fundamental way transistors have always been made.
Their engineers found better insulating properties — by a factor of 10 — in a class of materials called `high k' dielectric (`k' is what engineers call the dielectric constant).
They replaced silicon dioxide with hafnium, a rare earth element with atomic number 72 in the Periodic Table, and a material that is used in the control rods of nuclear reactors.
Metallic combo
They found that hafnium could not be made to work with poly silicon gate electrodes and decided to put the 'M' back into MOS. They came up with a metallic combo for the gate material (the exact combination is a secret).
At any rate, reworking the transistor with a high-k dielectric and returning to its roots in a metallic gate has helped Intel make a successful transition to 45 nanometer fabrication with a 20 per cent increase in the drive current and a five fold decrease in leakage.
The result, they can cram twice as many transistors on the 45 nm slab as they could at 65 nm. And cut switching power consumption by a third.
Radically different
The new processor family based on this radically different way of manufacturing transistors is being called `Penryn'— and it will ensure that Moore's Law (which predicted a doubling of transistors on a chip and consequent computational power, every 24 months) lives on.
Dr Moore himself has characterised it as the biggest change in transistor technology since the introduction of poly silicate gate MOS in the late 1960s.
At Beijing, I saw production wafers, 300 mm in diameter, containing thousands of the new 45 nm Penryn class chips — every chip now housing a billion transistors.
By year end, Intel plans to roll out dual and quad core (that is two and four processor cores to a chip) microprocessors in the new 45 nm process, in all three segments: server, desktop and portable PCs.
Prototype machines fuelled by these chips were up and working at the IDF. Intel had struck out into the future by a canny step back to the metallic origins of the transistor.
It is unrealistic to expect that Intel will remain alone for long, while getting past this significant obstacle in the long history of semiconductor manufacturing.
Competitors like AMD, Infineon, Freescale, Sony, Toshiba all have their own technology trails to get to 45 nm and beyond. IBM, has announced its own high-k metal gate technology that should reach the fabs in 2008.
`Garam hawa'
Texas Instruments has also said it has a high-k solution that it will be realising this year. Clearly `Back to the Future' is the way the semiconductor `garam hawa' is blowing this year.
Forty five nanometre technology and the consequent ability to put over a billion active components on every chip, will possibly kick start the tera scale computing initiatives of various players.
Intel's Indian engineers contributed nearly half the effort that went into its recently announced `teraflop on a chip' concept processor with 80 cores on board. Sometimes seeing is the only way to believing.
Just 46 watts
At the Beijing event, I saw Nitin Borkar, Head of Intel's Terascale project, put a machine fuelled by the 80-core chip through its paces — live. As the `flop' meter crossed the 1 tera flop (that is a trillion floating point operations a second) marker, the chip was drawing just 46 watts — less than a light bulb!
At 1.5 teraflops, the energy consumed was 93 watts and finally in a final burst of speed, Nitin had the computer cross the magic 2 tera flop mark dissipating less than 192 watts.
Did they say one teraflop on a chip? So yesterday! Already a month later, it looks more like two.
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